Python-based HDL
January 26th, 2006 | Tags: PL
LtU links to MyHDL, which translates from Python to Verilog. I can only assume that being able to use Python as a hardware description language absolutely demolishes Verilog in every way. The key idea is using Python generators (sort of like limited coroutines) to express hardware concurrency. If I’m not confused, it looks like generators (and coroutines) present an attractive way to describe other synchronous concurrent systems. DSP and synthesis code, for example, could use generators to deal with the multiple timescales involved in digital audio and with the state requirements of, e.g. synthesizer voices or digital filters.
I’m currently listening to Stand Up Tall from the album “Showtime” by Dizzee Rascal